What are PLDs (CPLD, FPGA)?


Programmable logic devices (PLDs) are reprogrammable integrated circuitsfor implementation of any digital functions.

Two important classes of PLDs are existing

  • CPLD = Complex programmable logic device
  • FPGA = Field programmable gate array

The basic idea is to build a combination of programmable AND/OR gates.
Several of these programmable gates on one integrated circuit are known as PLDs (= Programmable logic device).

In the combination of PLDs and Gate Array technology accrued FPGAs, which are more complex than CPLDs.

An FPGA is a regular structure of logic cells or modules and interconnect is under designer's complete control. This means the user can design, program and make changes ti his circuit whenever he wants.

Two type classes of FPGAs are existing

  • One time programmable (OTP) FPGAs use fuses-/anti-fuses to make permanent connections in the chip. Every time the designer make changes, he must throw away the chip. They keep their information after switch off the supply voltage.
  • SRAM-based FPGAs keep the information for the logic circuits and their interconnections in static RAM. The memory cells of the logic groups are thus LUTs (= Look up tables). They are very often reprogrammable, but they lost their informationen on switch off the supply voltage. Thats why the designer need a serial PROM or system memory with every SRAM FPGA.

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Virtex

The hardware of modern CPLDs and FPGAs is very complex meanwhile.
We use in our firm FPGAs and CPLDs of the company Firma XILINX.
» Overview

The CPLDs of the model ranges XC9500, CoolRunner and CoolRunner-II have up to 512 macro cells, up to 12 000 system gates, up to 192 programmable inputs/ outputs, maximal frequecy of 303 MHz at a low power consumption less than 100 µA.

The XILINX FPGAs include the production series Spartan and Virtex with up to 10 Mio. gates, 1,25 MB Block RAM, over 1000 programmable inputs/ outputs, up to 512 (18x18 bit) hardware multiplier, up to 20 DCMs (Digital Clock Manager)with up to 500 MHz, up to four 10/100/100 Ethernet MACs, up to 24 RocketIO Transceiver with 622 Mb/s to 11,1 Gb/s and up to 4 hardware IBM PowerPCs 405 per integrated circuit.
» Schematic structure of a Spartan FPGA